One of the. characteristics of a phase locked loop (PLL) is the locking or settling time; i.e. the time it takes the PLL to lock to a certain input signal or to respond to frequency and phase steps. In general, the locking time is dependent on the PLL's loop bandwidth, the lower the loop bandwidth the longer it takes the PLL to lock. It is generally accepted in the art that the term “settle” is defined as arriving within a certain relative or absolute accuracy.
PLLs are not only used in telecommunications applications, but also in measurement technology (for instance optical telemetry), control of motors, medical equipment and the like. Also in those applications, the phase and frequency step responses are important design considerations.
One of the most widely used types of PLL is the type II PLL. A type II PLL will lock with zero frequency offset and zero phase offset while a type I PLL will only achieve zero frequency offset when in lock.
FIG. 1 shows a typical type II PLL, consisting of a phase detector, a loop filter, a controlled oscillator and a feedback loop with a divider. In FIG. 1, a phase detector 10 is connected to a pair of multipliers 12, 18. The multiplier 12 is connected to the input of a controlled oscillator 16, for example a digital controlled oscillator. The loop filter of a type II PLL has an integrator 20 to achieve the zero phase offset when the PLL is in lock. The output of the multiplier 18 is connected to the integrator 20. The multipliers introduce the P factor and the I factor in a manner known per se. A feedback loop is provided from the output of the controlled oscillator 16 through proportional unit 30 to the second input of the phase detector 10.
When the PLL is locking to the input signal, the phase detector's output signal is integrated in the loop filter's integrator and the integrator's output signal is combined with the phase detector's output signal to the control signal of the controlled oscillator. The path from the phase detector to adder where the integrator value is added is often called the proportional path. The integrating path and the proportional path have separate scaling factors. The proportional path factor mainly determines the loop filter bandwidth while the ratio of proportional path and the integrating path factor determines the damping of the PLL.
The use of I and P factors are known in the art and control the performance of the PLL. The output of the integrator is added to the output of the phase detector multiplied by the P factor to determine the frequency of the controlled oscillator. When the phase difference is zero, i.e. on a phase hit, the frequency of the controlled oscillator is determined by the output of the integrator.
When the type II PLL is locked with a zero phase offset, the phase detector generates a zero output value. If the PLL's input signal has a frequency offset with respect to the PLL's centre frequency, then the integrator in the loop filter must generate the control signal that offsets the controlled oscillator from the PLL's centre frequency. So when the type II PLL is locked, the integrator in the loop filter contains the frequency offset.
The ratio of the proportional and integrator path factors determines the damping and thereby the response of the PLL with respect to phase and frequency transients. If the PLL has a small damping i.e. is underdamped, the integrating path factor is relatively large, it will respond to input transients with large overshoots in the time domain and it will show peaking in the jitter transfer function in the frequency domain. If the PLL has a large damping i.e. is overdamped, the integrating path factor is relatively small, it will respond to input transients with no or barely any overshoot in the time domain and has practically no peaking in the frequency domain jitter transfer function.
The amount of overshoot and peaking that can be tolerated is usually determined by the application. In many applications, relatively large overshoot and peaking is simply not acceptable. In the case of PLL's for telecommunications applications, telecom standards define how much peaking is allowed, for example 2% or 0.2 dB. These numbers are quite small.
When a frequency step is applied to a type II PLL, the damping determines how fast the integrator in the loop filter will settle to the value corresponding to the new frequency offset. The larger the damping, the longer the settling time of the integrator and thereby the longer it takes the PLL to achieve lock. U.S. Pat. No. 6,784,706 to Van Der Valk issued on Aug. 31, 2004 describes the relationship between the locking time, the bandwidth and the damping for type II PLLs. From this analysis follows that PLL's with a low bandwidth and a damping that limits the peaking to 0.2 dB take a long time to lock if no special measures are taken.
Various telecom standards restrict the maximum locking time of PLL with a very low bandwidth. For example Telcordia GR-1244-CORE states that the locking time of a Sonet Minimum Clock (SMC) compliant PLL with a bandwidth of 0.1 Hz must be locked within 100 seconds. A Stratum 3E compliant PLL with a bandwidth of 1 mHz must be locked within 700 seconds. These numbers cannot be met without special measures like temporarily increasing the bandwidth, decreasing the damping or both.
A common method to decrease the locking time is to temporarily increase the PLL's bandwidth and decrease the damping. Several PLL circuits for telecom applications use this approach. The disadvantage of increasing the PLL's bandwidth is that more phase noise that may be present on the input signal is not attenuated as much before propagating to the output of the PLL. Decreasing the damping of the PLL will cause a larger overshoot on the output signal. These effects degrade the quality of the output signal or may even cause disruptions in the network and are therefore undesirable.
The method disclosed in U.S. Pat. No. 6,784,706 monitors the phase offset during the locking process. When the phase offset is zero just before the PLL's output clock frequency overshoots the target frequency, the proportional value is added to the integrator and in principle the PLL is (close to) lock. However, this method is sensitive to wander and jitter on the input reference clock and can therefore copy a relatively large frequency error to the integrator.
Phase noise (wander and jitter) on the measured reference can degrade the accuracy of the measured frequency offset. If the PLL uses the same local oscillator clock to generate its output clock, the accuracy of the local clock is a common mode error for both the reference monitor's frequency estimate and the PLL's frequency offset.
In FIG. 7 the line represents the normal phase response, which shows some overshoot and thus carries quite a lot of settling.